Recently, a clock frequency of an LSI chip reaches a GHz zone. However, a frequency of an outside-chip line for exchanging a signal has been up to only 533 MHZ (Rambus protocol), and a bandwidth for receiving a signal into an LSI has not been sufficient for the requirement of the LSI. In order to make the signal processing of the LSI smooth, a logic chip and memory chip are provided with a cache memory to compensate a narrow bandwidth. However, it is necessary not only to provide a large cache memory area, but also to perform an additional address calculation, thereby making architecture complex.
If it is possible to ensure an I/O bandwidth matched with the LSI clock, it is not necessary to provide the cache memory, thereby making architecture simple. In a basic digital system, a chip I/O is essentially the same as the number of processing bits in the chip. In order to match the bandwidth, the chip clock needs to be the same as a transmission clock of the I/O bus. As the chip clock enters a GHZ band, it is necessary to improve the bus clock. Even though a transmission line, i.e. a basic configuration of the bus, has the specific characteristic, it is still difficult to pass a GHZ band clock. In other words, in order to make the GHZ transmission possible, it is necessary to make all of a driver, a receiver, and a packaging structure including the driver and receiver ready for passing a high-speed signal.
On the other hand, in a forecast of the future chip, Intel Corporation has released a MOS structure with a 20 nm gate length at the 2001 Symposium on VLSI Technology (2001. 6 Kyoto), claiming that it will be possible to process a 20 GHZ digital signal (forecasted by 2007). However, in order to pass through a digital signal between 20 to 50 GHZ through a wiring in a chip with a 10 mm square, it is necessary to design a new configuration quite different from a concept of an RC charge and discharge circuit. In other words, in order to provide a unified environment over an entire system, it is necessary to design a totally new system.